UltraSparc I: a four-issue processor supporting multimedia

Issuing four instructions per cycle, this wo rksta tio n/server processor uses the Visual Instruction Set and a nonblocking memo y system to accelerate multimedia applications. Itrasparc I is a second-generation superscalar processor. It is a high-performance, highly integrated, four-issue superscalar processor based on the Sparc Version 9 64-bit RISC architecture.' We have extended the core instruction set to include graphics instructions that provide the most common operations related to two-dimensional image processing; two-and three-dimensional graphics and image compression algorithms; and parallel operations on pixel data with 8-, 16-, and 32-bit coni-ponents. Additional, new memory access instructions support the very high bandwidth requirements typical of graphics and multi-media applications. A 200-MHz UltraSparc with a 2-Mbyte external cache delivers an estimated 322 SPECint92 and 462 SPEGfp92. UltraSparc can decode broadcast-quality MPEG-2 streams and move data to or from main memory at a rate of 1.6 Gbytes/s peak or 700 Mbytes/s sustained. UltraSparc can sustain the execution of up to four instructions per cycle, even in the presence of conditional branches and cache misses. This is due mainly to the decoupled aspect of the units feeding instructions and data to the rest of the pipeline. Those instructions predicted to execute issue in program order to multiple functional units, execute in parallel, and, for added parallelism, can complete out of order. To further increase the number of instructions executed per cycle, instructions from two basic blocks (that is, instructions before and after a conditional branch) can issue in the same group. The UltraSparc die (Figure 1) includes a lG-Kbyte, pseudo-two-way set-asso-ciative instruction cache; * a 64-entry, fully associative instruction translation look-aside buffer (TLB); * a lG-Kbyte, direct-mapped write-through data cache; a 64-entry, fully associative data translation look-aside buffer, 0 nine functional units, a nine-entry-deep load buffer,-an eight-entry-deep store buffer, and-logic to control the 144-bit external bus The first implementation of UltraSparc uses a 0.5-micron process with four layers of metal, resulting in a 310-mm2 die composed of 5.2 million transistors. The 521-pin chip typically dissipates 28W at 167 MHz. Microarchitecture UltraSparc s design dedicates only 1 6 mil lion transistors to the basic data arrays of the 16-Kbyte instruction cache and the 16-Kbyte data cache, which cover a combined area of around 15 percent of the chip We could have dedicated an area two-or three-times larger than that to caches, 100 Kbytes of on-chip cache are possible using 0 5-micron technology This, however, …